...simulators for verifying simple designs;
Work experience with mixed-signal test benches, SVA, functional coverage, constrained randomization and UPF
Basic knowledge of any HDL for modeling such as Verilog-AMS; SV-RNM is highly desirable, UVM knowledge is a plus...
...components, testcases which are scalable and portable across various projects and platforms;
Define verification strategy (constraint random, formal, directed etc.) for digital or mixed-signal IP/Subsystem and SoC verification;
Work in different verification methodologies...
...and Matlab are a plus.
~ Gate level Simulation debug and usage of power extraction tools is a plus
~ Experienced withconstrained-random verificationenvironment and flow build-up with UVM, Coverage-Driven verification methodology
~ Experienced with Assertions like System...
...digital circuit designs from definition to implementation
Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.
Own some or all aspects of the Verification flow from initial test...
...IP features.
Write/Implement/Review Test Plans.
Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.
Own some or all aspects of the Verification flow from initial test...
...standard tools and technologies.
• Proficient in developing unit and subsystem level test benches using SV/UVM methodology.
• Constrained random and Metrics driven verification.
• Experienced with C model integration and scorebording
• FW code integration verification
•...
...defining verification strategies for critical features.
Work towards quality metric convergence and sign-off using coverage-driven random and directed-testing techniques.
Qualifications and Experience:
~ Bachelor Degree in Electrical Engineering or equivalent
~5...